2

A kind of Multistage Interconnection Networks with multiple paths

Year:
1996
Language:
english
File:
PDF, 674 KB
english, 1996
8

IDDT Testing versus IDDQ Testing

Year:
1998
Language:
english
File:
PDF, 54 KB
english, 1998
12

Design & Test Education in Asia

Year:
2004
Language:
english
File:
PDF, 77 KB
english, 2004
21

Boolean process

Year:
1997
Language:
english
File:
PDF, 479 KB
english, 1997
22

Short-time scaling of variable ordering of OBDDs

Year:
1997
Language:
english
File:
PDF, 386 KB
english, 1997
23

Editor’s note

Year:
2001
Language:
english
File:
PDF, 125 KB
english, 2001
24

An analytical delay model

Year:
1999
Language:
english
File:
PDF, 1.12 MB
english, 1999
25

Editor’s note

Year:
2000
Language:
english
File:
PDF, 123 KB
english, 2000
26

Editor’s note

Year:
2000
Language:
english
File:
PDF, 131 KB
english, 2000
27

A novel RTL behavioral description based ATPG method

Year:
2003
Language:
english
File:
PDF, 1.15 MB
english, 2003
29

Node grouping in system-level fault diagnosis

Year:
2001
Language:
english
File:
PDF, 517 KB
english, 2001
30

IDDT: Fundamentals and test generation

Year:
2003
Language:
english
File:
PDF, 881 KB
english, 2003
31

Path sensitization

Year:
1997
Language:
english
File:
PDF, 623 KB
english, 1997
32

Why RTL ATPG?

Year:
2002
Language:
english
File:
PDF, 395 KB
english, 2002
36

Reduction of Number of Paths to be Tested in Delay Testing

Year:
2000
Language:
english
File:
PDF, 67 KB
english, 2000
39

A built-in test pattern generator

Year:
1986
Language:
english
File:
PDF, 451 KB
english, 1986
40

Easy test generation PLAs

Year:
1987
Language:
english
File:
PDF, 457 KB
english, 1987
41

Product-oriented test-pattern generation for Programmable Logic Arrays

Year:
1990
Language:
english
File:
PDF, 611 KB
english, 1990
42

Guest editor’s introduction: Fault—Tolerant Computing

Year:
1990
Language:
english
File:
PDF, 143 KB
english, 1990
43

A fault-tolerant and heuristic routing algorithm for faulty hypercubes

Year:
1995
Language:
english
File:
PDF, 544 KB
english, 1995
44

Pseudo-random test generation for large combinational circuits

Year:
1992
Language:
english
File:
PDF, 560 KB
english, 1992
45

Aliasing errors in Parallel Signature Analyzers

Year:
1990
Language:
english
File:
PDF, 708 KB
english, 1990
47

Canonical conformal mapping for high genus surfaces with boundaries

Year:
2012
Language:
english
File:
PDF, 2.10 MB
english, 2012