An Implementation for Test-Time Reduction in VLIW...

Journal of Electronic Testing 2002 / 04 Vol. 18; Iss. 2

An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures

V.A. Zivkovic, R.J.W.T. Tangelder, H.G. Kerkhoff
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Volume:
18
Language:
english
Pages:
10
DOI:
10.1023/a:1014901829507
Date:
April, 2002
File:
PDF, 314 KB
english, 2002
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