Tests for small gate delay faults in combinational circuits and a test generation method
Hiroshi Takahashi, Takashi Watanabe, Toshiyuki Matsunaga, Yuzo TakamatsuVolume:
28
Year:
1997
Pages:
9
DOI:
10.1002/(sici)1520-684x(19970615)28:63.0.co;2-k
File:
PDF, 1.08 MB
1997