Memory Power Reduction for High-Speed Implementation of...

Journal of Signal Processing Systems 2003 / 03 Vol. 33; Iss. 3

Memory Power Reduction for High-Speed Implementation of Turbo Codes

B. Bougard, L. van der Perre, F. Maessen, A. Giulietti, V. Derudder, F. Catthoor
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Volume:
33
Language:
english
Pages:
10
DOI:
10.1023/a:1022132031284
Date:
March, 2003
File:
PDF, 281 KB
english, 2003
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