4–kbit bipolar RAM with on–chip address latch function

Electronics and Communications in Japan (Part II: Electronics)) 1987 Vol. 70; Iss. 10

4–kbit bipolar RAM with on–chip address latch function

Hiroaki Nambu, Kazuo Kanetani, Kunihiko Yamaguchi, Noriyuki Homma, Hideo Todokoro, Kazuhiro Akimoto, Katsumi Ogiue
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Volume:
70
Year:
1987
Language:
english
Pages:
11
DOI:
10.1002/ecjb.4420701006
File:
PDF, 814 KB
english, 1987
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