A graph partitioning heuristic for the parallel...

Annals of Operations Research 1994 Vol. 50; Iss. 1

A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits

Alexandre A. Andreatta, Celso C. Ribeiro
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Volume:
50
Year:
1994
Language:
english
Pages:
36
DOI:
10.1007/bf02085633
File:
PDF, 2.36 MB
english, 1994
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