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A dividing ratio changeable digital PLL with low jitter using a multiphase clock divider
Kuniaki Fujimoto, Mitsutoshi Yahara, Hirofumi SasakiVolume:
94
Year:
2011
Language:
english
Pages:
8
DOI:
10.1002/ecj.10340
File:
PDF, 751 KB
english, 2011