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0.2-μm fully-self-aligned Y-shaped gate HJFET's with reduced gate-fringing capacitance fabricated using collimated sputtering and electroless Au-plating
Wada, S., Tokushima, M., Fukaishi, M., Matsuno, N., Yano, H., Hida, H., Maeda, T.Volume:
45
Year:
1998
Language:
english
Pages:
7
DOI:
10.1109/16.704360
File:
PDF, 259 KB
english, 1998