A Triple Modular Redundancy Technique Providing...

IEEE Transactions on Computers 1986 Vol. C-35; Iss. 7

A Triple Modular Redundancy Technique Providing Multiple-Bit Error Protection Without Using Extra Redundancy

Van Gils, W.J.
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Volume:
C-35
Year:
1986
Language:
english
Pages:
9
DOI:
10.1109/tc.1986.1676803
File:
PDF, 2.81 MB
english, 1986
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