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Gate Capacitance Reduction Due to the Inversion Layer in High- /Metal Gate Stacks Within a Subnanometer EOT Regime
Iijima, R., Edge, L.F., Ariyoshi, K., Bruley, J., Paruchuri, V., Takayanagi, M.Volume:
58
Year:
2011
Language:
english
Pages:
10
DOI:
10.1109/ted.2011.2106786
File:
PDF, 405 KB
english, 2011