EMC Assessment at Chip and PCB Level: Use of the ICEM Model...

IEEE Transactions on Electromagnetic Compatibility 2007 Vol. 49; Iss. 1

EMC Assessment at Chip and PCB Level: Use of the ICEM Model for Jitter Analysis in an Integrated PLL

Jean-Luc Levant, Mohamed Ramdani, Richard Perdriau, M'hamed Drissi
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Volume:
49
Year:
2007
Language:
english
Pages:
10
DOI:
10.1109/temc.2006.888181
File:
PDF, 2.13 MB
english, 2007
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