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[IEEE IEEE International Electron Devices Meeting - San Francisco, CA, USA (8-11 Dec. 2002)] Digest. International Electron Devices Meeting, - A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell
Thompson, S., Anand, N., Armstrong, M., Auth, C., Arcot, B., Alavi, M., Bai, P., Bielefeld, J., Bigwood, R., Brandenburg, J., Buehler, M., Cea, S., Chikarmane, V., Choi, C., Frankovic, R., Ghani, T.,Year:
2002
Language:
english
Pages:
4
DOI:
10.1109/iedm.2002.1175779
File:
PDF, 276 KB
english, 2002