Fast Power- and Slew-Aware Gated Clock Tree Synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2012 Vol. 20; Iss. 11

Fast Power- and Slew-Aware Gated Clock Tree Synthesis

Lu, J., Chow, W.-K., Sham, C.-W.
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Volume:
20
Year:
2012
Language:
english
Pages:
1
DOI:
10.1109/tvlsi.2011.2168834
File:
PDF, 1.35 MB
english, 2012
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