A High Speed Low Power CAM With a Parity Bit and...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2013 / 01 Vol. 21; Iss. 1

A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing

Do, Anh-Tuan, Chen, Shoushun, Kong, Zhi-Hui, Yeo, Kiat Seng
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Volume:
21
Language:
english
Pages:
6
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/tvlsi.2011.2178276
Date:
January, 2013
File:
PDF, 960 KB
english, 2013
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