FPGA Implementation of the Generalized Delayed Signal...

IEEE Transactions on Industrial Electronics 2013 / 02 Vol. 60; Iss. 2

FPGA Implementation of the Generalized Delayed Signal Cancelation—Phase Locked Loop Method for Detecting Harmonic Sequence Components in Three-Phase Signals

Nascimento, Paulo S. B., de Souza, Helber E. P., Neves, Francisco A. S., Limongi, Leonardo R.
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Volume:
60
Language:
english
Pages:
14
Journal:
IEEE Transactions on Industrial Electronics
DOI:
10.1109/tie.2012.2206350
Date:
February, 2013
File:
PDF, 1.32 MB
english, 2013
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