VLSI architecture of signal processing chip set for 42-inch DC PDP HDTV receiver
Kokubun, H., Takano, Y., Yamamoto, T., Ishii, K., Kurita, T.Volume:
44
Year:
1998
Language:
english
DOI:
10.1109/30.713184
File:
PDF, 853 KB
english, 1998