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A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface
Tyhach, J., Wang, B., Sung, C., Huang, J., Nguyen, K., Xiaobao Wang, Yan Chong, Pan, P., Kim, H., Rangan, G., Tzung-Chin Chang, Tan, J.Volume:
40
Year:
2005
Language:
english
DOI:
10.1109/jssc.2005.852156
File:
PDF, 1.51 MB
english, 2005