"Split ADC" architecture for deterministic...

IEEE Journal of Solid-State Circuits 2005 Vol. 40; Iss. 12

"Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC

McNeill, J., Coln, M.C.W., Larivee, B.J.
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Volume:
40
Year:
2005
Language:
english
DOI:
10.1109/jssc.2005.856291
File:
PDF, 799 KB
english, 2005
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