Design of Low-Loss Transmission Lines in Scaled CMOS by...

IEEE Journal of Solid-State Circuits 2009 Vol. 44; Iss. 9

Design of Low-Loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations

Repossi, M., Eyssa, W., Vecchi, F., Arcioni, P., Svelto, F.
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Volume:
44
Year:
2009
Language:
english
DOI:
10.1109/jssc.2009.2023277
File:
PDF, 1.34 MB
english, 2009
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