A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache
Barth, J., Plass, D., Nelson, E., Hwang, C., Fredeman, G., Sperling, M., Mathews, A., Kirihata, T., Reohr, W.R., Nair, K., Nianzheng CaonVolume:
46
Year:
2011
Language:
english
DOI:
10.1109/jssc.2010.2084470
File:
PDF, 2.37 MB
english, 2011