A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and...

IEEE Journal of Solid-State Circuits 2012 Vol. 47; Iss. 6

A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces

Hyun-Woo Lee, Hoon Choi, Beom-Ju Shin, Kyung-Hoon Kim, Kyung-Whan Kim, Jaeil Kim, Kwang-Hyun Kim, Jong-Ho Jung, Jae-Hwan Kim, Eun-Young Park, Jong-Sam Kim, Jong-Hwan Kim, Jin-Hee Cho, Namgyu Rye, Jun-
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Volume:
47
Year:
2012
Language:
english
DOI:
10.1109/jssc.2012.2191027
File:
PDF, 3.79 MB
english, 2012
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