Test-Length and TAM Optimization for Wafer-Level Reduced...

Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs

Bahukudumbi, S., Chakrabarty, K.
How much do you like this book?
What’s the quality of the file?
Download the book for quality assessment
What’s the quality of the downloaded files?
Volume:
28
Year:
2009
Language:
english
DOI:
10.1109/tcad.2008.2009150
File:
PDF, 438 KB
english, 2009
Conversion to is in progress
Conversion to is failed