Leakage Minimization of Digital Circuits Using Gate Sizing...

Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations

Bhardwaj, S., Vrudhula, S.
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Volume:
27
Year:
2008
Language:
english
DOI:
10.1109/tcad.2008.916341
File:
PDF, 614 KB
english, 2008
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