A Unified Approach for Full Chip Statistical Timing and...

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2008 Vol. 27; Iss. 10

A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations

Bhardwaj, S., Vrudhula, S., Goel, A.
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Volume:
27
Year:
2008
Language:
english
DOI:
10.1109/tcad.2008.927671
File:
PDF, 951 KB
english, 2008
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