A wide-range delay-locked loop with a fixed latency of one clock cycle
Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang, Shen-Iuan LiuVolume:
37
Year:
2002
Language:
english
DOI:
10.1109/jssc.2002.800922
File:
PDF, 315 KB
english, 2002