Analysis and optimization of nanometer CMOS circuits for...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2006 Vol. 14; Iss. 5

Analysis and optimization of nanometer CMOS circuits for soft-error tolerance

Dhillon, Y.S., Diril, A.U., Chatterjee, A., Singh, A.D.
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Volume:
14
Year:
2006
Language:
english
DOI:
10.1109/tvlsi.2006.876104
File:
PDF, 1.08 MB
english, 2006
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