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Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process
Hazucha, P., Karnik, T., Walstra, S., Bloechel, B.A., Tschanz, J.W., Maiz, J., Soumyanath, K., Dermer, G.E., Narendra, S., De, V., Borkar, S.Volume:
39
Year:
2004
Language:
english
DOI:
10.1109/jssc.2004.831449
File:
PDF, 891 KB
english, 2004