[IEEE 2007 International Semiconductor Device Research Symposium - College Park, MD, USA (2007.12.12-2007.12.14)] 2007 International Semiconductor Device Research Symposium - Vertical silicon-on-nothing FET: Threshold voltage calculation using compact capacitance model
Svilicic, Boris, Jovanovic, Vladimir, Suligoj, TomislavYear:
2007
Language:
english
DOI:
10.1109/isdrs.2007.4422545
File:
PDF, 251 KB
english, 2007