A 5-bit 3.2-GS/s Flash ADC With a Digital Offset...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2010 Vol. 18; Iss. 3

A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme

Ying-Zu Lin, Cheng-Wu Lin, Soon-Jyh Chang
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Volume:
18
Year:
2010
Language:
english
DOI:
10.1109/tvlsi.2009.2013628
File:
PDF, 418 KB
english, 2010
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