Large Within-Die Gate Delay Variations in Sub-Threshold...

IEEE Transactions on Circuits and Systems II: Express Briefs 2012 / 12 Vol. 59; Iss. 12

Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature

Takahashi, Ryo, Takata, Hidehiro, Yasufuku, Tadashi, Fuketa, Hiroshi, Takamiya, Makoto, Nomura, Masahiro, Shinohara, Hirofumi, Sakurai, Takayasu
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Volume:
59
Language:
english
Journal:
IEEE Transactions on Circuits and Systems II: Express Briefs
DOI:
10.1109/tcsii.2012.2231038
Date:
December, 2012
File:
PDF, 234 KB
english, 2012
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