A 40-nm Sub-Threshold 5T SRAM Bit Cell With Improved Read...

IEEE Transactions on Circuits and Systems II: Express Briefs 2012 / 12 Vol. 59; Iss. 12

A 40-nm Sub-Threshold 5T SRAM Bit Cell With Improved Read and Write Stability

Teman, Adam, Mordakhay, Anatoli, Mezhibovsky, Janna, Fish, Alexander
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Volume:
59
Language:
english
Journal:
IEEE Transactions on Circuits and Systems II: Express Briefs
DOI:
10.1109/tcsii.2012.2231020
Date:
December, 2012
File:
PDF, 825 KB
english, 2012
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