Area-Efficient Scalable MAP Processor Design for...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2011 Vol. 19; Iss. 2

Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding

Chen-Hung Lin, Chun-Yu Chen, An-Yeu Wu
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Volume:
19
Year:
2011
Language:
english
DOI:
10.1109/tvlsi.2009.2032553
File:
PDF, 2.53 MB
english, 2011
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