A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2011 Vol. 19; Iss. 9

A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology

Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Suki Kim
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Volume:
19
Year:
2011
Language:
english
DOI:
10.1109/tvlsi.2010.2053395
File:
PDF, 1.57 MB
english, 2011
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