![](/img/cover-not-exists.png)
A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology
Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Suki KimVolume:
19
Year:
2011
Language:
english
DOI:
10.1109/tvlsi.2010.2053395
File:
PDF, 1.57 MB
english, 2011