On–chip multibit–test scheme for VLSI memories

Electronics and Communications in Japan (Part II: Electronics)) 1988 Vol. 71; Iss. 9

On–chip multibit–test scheme for VLSI memories

Hideto Hidaka, Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Katsumi Dosaka, Yasumasa Nishimura, Tsutomu Yoshihara
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Volume:
71
Year:
1988
Language:
english
DOI:
10.1002/ecjb.4420710909
File:
PDF, 628 KB
english, 1988
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