Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems
Vasudevan, S., Viswanath, V., Sumners, R.W., Abraham, J.A.Volume:
56
Year:
2007
Language:
english
DOI:
10.1109/tc.2007.1073
File:
PDF, 2.39 MB
english, 2007