A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip...

IEEE Journal of Solid-State Circuits 2003 Vol. 38; Iss. 5

A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

Chang, K.-Y.K., Wei, J., Huang, C., Li, S., Donnelly, K., Horowitz, M., Yingxuan Li, Sidiropoulos, S.
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Volume:
38
Year:
2003
Language:
english
Journal:
IEEE Journal of Solid-State Circuits
DOI:
10.1109/JSSC.2003.810045
File:
PDF, 1.63 MB
english, 2003
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