Design of a low-power 32 K CMOS programmable delay-line...

IEEE Journal of Solid-State Circuits 1990 Vol. 25; Iss. 1

Design of a low-power 32 K CMOS programmable delay-line memory

Dejhan, K., Demassieux, N., Colavin, O., Galisson, A., Artieri, A., Jutand, F.
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Volume:
25
Year:
1990
Language:
english
DOI:
10.1109/4.50309
File:
PDF, 561 KB
english, 1990
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