A 3.8-ns CMOS 16×16-b multiplier using complementary...

IEEE Journal of Solid-State Circuits 1990 Vol. 25; Iss. 2

A 3.8-ns CMOS 16×16-b multiplier using complementary pass-transistor logic

Yano, K., Yamanaka, T., Nishida, T., Saito, M., Shimohigashi, K., Shimizu, A.
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Volume:
25
Year:
1990
Language:
english
DOI:
10.1109/4.52161
File:
PDF, 650 KB
english, 1990
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