A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an...

IEEE Journal of Solid-State Circuits 1998 Vol. 33; Iss. 11

A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter

Matsuura, T., Nara, T., Komatsu, T., Imaizumi, E., Horita, R., Katsu, H., Suzumura, S., Sato, K.
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Volume:
33
Year:
1998
Language:
english
DOI:
10.1109/4.726586
File:
PDF, 350 KB
english, 1998
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