A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced...

IEEE Journal of Solid-State Circuits 2001 Vol. 36; Iss. 5

A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity

Kye-Hyun Kyung, Hi-Choon Lee, Ki-Whan Song, Ho-Sung Song, Keewook Jung, Joon-Seo Moon, Byoung-Sul Kim, Sung-Burn Cho, Changhyun Kim, Soo-In Cho
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Volume:
36
Year:
2001
Language:
english
DOI:
10.1109/4.918910
File:
PDF, 336 KB
english, 2001
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