Universal-Vdd 0.65-2.0-V 32-kB cache using a...

IEEE Journal of Solid-State Circuits 2001 Vol. 36; Iss. 11

Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell

Osada, K., Jinuk Luke Shin, Khan, M., Liou, Y., Wang, K., Shoji, K., Kuroda, K., Ikeda, S., Ishibashi, K.
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Volume:
36
Year:
2001
Language:
english
DOI:
10.1109/4.962296
File:
PDF, 311 KB
english, 2001
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