Post-layout timing simulation of CMOS circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 1993 Vol. 12; Iss. 8

Post-layout timing simulation of CMOS circuits

Deschacht, D., Robert, M., Azemard-Crestani, N., Auvergne, D.
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Volume:
12
Year:
1993
Language:
english
DOI:
10.1109/43.238609
File:
PDF, 736 KB
english, 1993
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