A bipartition-codec architecture to reduce power in...

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2001 Vol. 20; Iss. 2

A bipartition-codec architecture to reduce power in pipelined circuits

Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Kun-Lin Tsai
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Volume:
20
Year:
2001
Language:
english
DOI:
10.1109/43.908477
File:
PDF, 167 KB
english, 2001
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