![](/img/cover-not-exists.png)
Optimized ESD protection circuits for high-speed MOS/VLSI
Fujishin, E., Garrett, K., Levis, M.P., Motta, R.F., Hartranft, M.Volume:
20
Year:
1985
Language:
english
DOI:
10.1109/jssc.1985.1052350
File:
PDF, 540 KB
english, 1985