An experimental 4-Mbit CMOS EEPROM with a NAND-structured...

IEEE Journal of Solid-State Circuits 1989 Vol. 24; Iss. 5

An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell

Momodomi, M., Itoh, Y., Shirota, R., Iwata, Y., Nakayama, R., Kirisawa, R., Tanaka, T., Aritome, S., Endoh, T., Ohuchi, K., Masuoka, F.
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Volume:
24
Year:
1989
Language:
english
DOI:
10.1109/jssc.1989.572587
File:
PDF, 842 KB
english, 1989
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