An all-digital phase-locked loop for high-speed clock...

IEEE Journal of Solid-State Circuits 2003 Vol. 38; Iss. 2

An all-digital phase-locked loop for high-speed clock generation

Ching-Che Chung, Chen-Yi Lee
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Volume:
38
Year:
2003
Language:
english
DOI:
10.1109/jssc.2002.807398
File:
PDF, 414 KB
english, 2003
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