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Loop-based interconnect modeling and optimization approach for multigigahertz clock network design
Xuejue Huang, Restle, P., Bucelot, T., Yu Cao, Tsu-Jae King, Chenming HuVolume:
38
Year:
2003
Language:
english
DOI:
10.1109/jssc.2002.808313
File:
PDF, 706 KB
english, 2003