A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet
Rong-Jyi Yang, Shang-Ping Chen, Shen-Iuan LiuVolume:
39
Year:
2004
Language:
english
DOI:
10.1109/jssc.2004.831809
File:
PDF, 561 KB
english, 2004