IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing
1998 Vol. 45; Iss. 12
An 8-bit CMOS 3.3-V 65-MHz digital-to-analog converter with a symmetric two-stage current cell matrix architecture
Ji Hyun Kim, Kwang Sub YoonVolume:
45
Year:
1998
Language:
english
Journal:
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
DOI:
10.1109/82.746683
File:
PDF, 397 KB
english, 1998