X-masking during logic BIST and its impact on defect...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2006 / 02 Vol. 14; Iss. 2

X-masking during logic BIST and its impact on defect coverage

Yuyi Tang,, Wunderlich, H.-J., Piet Engelke,, Polian, I., Becker, B., Schloffel, J., Hapke, F., Wittke, M.
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Volume:
14
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2005.863742
Date:
February, 2006
File:
PDF, 860 KB
english, 2006
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